1. Field of the Invention
The present invention relates to an image display apparatus and an image display method. More particularly, the present invention can be applied to an image display apparatus capable of switching the operation from an analog driving mode to a memory mode and vice versa. The present invention allows the opening window of a liquid-crystal cell employed in a pixel cell to be sufficiently widened by making use of a simple configuration utilizing switch circuits each used for connecting a pixel unit to a signal line in the analog driving mode also as switch circuits each used for connecting a liquid-crystal cell employed in a pixel unit to a memory unit employed in the same pixel unit in the memory mode.
2. Description of the Related Art
The existing liquid-crystal display apparatus includes a display section. The display section displays an image on pixel units laid out to form a matrix on the display section. Each of the pixel units includes one of liquid-crystal cells forming the displayed image and a driving circuit which is a circuit for driving the liquid-crystal cells. The display section of the liquid-crystal display apparatus is provided with scan lines each associated with one of pixel rows composing the matrix. In addition, the display section is also provided with signal lines each associated with one of pixel columns composing the matrix. Each of the scan lines crosses the signal lines. In the liquid-crystal display apparatus, a scan signal appearing on a scan line controls pixel units on a row associated with the scan line. The scan lines sequentially control their respective rows. A signal line is connected to liquid-crystal cells each included in one of pixel units on a column associated with the signal line. The gradation of a liquid-crystal cell is determined by the level of a signal appearing on a signal line connected to the liquid-crystal cell. With such a configuration, the liquid-crystal display apparatus displays a desired image. In the following description, the mode of controlling the gradation of a liquid-crystal cell in accordance with the level of a signal appearing on a signal line connected to the liquid-crystal cell is referred to as the analog driving mode cited above.
In accordance with a technology disclosed in Japanese Patent Laid-open No. Hei 9-243995, on the other hand, there is provided a configuration in which each pixel unit is provided with a memory unit used for recording data and the pixel unit is driven in accordance with the data recorded in the memory unit. In the following description, this mode of driving a pixel unit in accordance with data recorded in a memory unit associated with the pixel unit is referred to as the memory mode mentioned above. In the memory mode, once a gradation of each pixel unit has been set, a process to set a gradation for each pixel unit is no longer required. Thus, the power consumption is low in comparison with the analog driving mode.
By the way, a configuration allowing both the memory mode and the analog driving mode to be adopted is considered to be a configuration providing convenience. To put it concretely, in a typical configuration, the analog driving mode is selected for displaying moving and still images whereas the memory mode is selected for displaying monochrome texts. With such a configuration, multi-gradation moving and still images can be displayed at a low power consumption. In the following description, a system allowing both the memory mode and the analog driving mode to be adopted is referred to as a hybrid system.
In the hybrid system, as shown in FIG. 23, each pixel unit 1 provided with a memory unit 3 used in the memory mode has a configuration including a changeover switch circuit for switching the gradation setting operation from the memory mode to the analog driving mode and vice versa and it is conceivable to configure a driving circuit for driving scan lines and a driving circuit for driving signal lines in conformity with the configuration of the pixel unit 1.
To put it concretely, NMOS transistors Q1 and Q2 compose a switch circuit adopting a double-gate technique. This switch circuit is a switch for selecting the analog driving mode. A gate signal DATEA turns on the NMOS transistors Q1 and Q2. The NMOS transistors Q1 and Q2 put in an on state connect a signal line SIG to a liquid-crystal cell 2 and a holding capacitor Cs. As shown by a dashed-line arrow in FIG. 23, in the analog driving mode, an electric potential appearing on a specific one of the terminals of the liquid-crystal cell 2 and an electric potential appearing on a specific one of the terminals of the holding capacitor Cs are each set at the level of a signal appearing on the signal line SIG. The gradation of the liquid-crystal cell 2 is thus determined by the level of a signal appearing on the signal line SIG. It is to be noted that the other terminal of the holding capacitor Cs is connected to a scan line which is connected to a CS driving circuit. The CS driving circuit asserts a pre-charging driving signal CS related to pre-charge processing on the scan line as shown in FIG. 24A. The other terminal of the liquid-crystal cell 2 is referred to as a common electrode of the liquid-crystal cell 2. The common electrode is connected to the common electrodes of liquid-crystal cells 2 each employed in another pixel unit 1 not shown in the figure. A driving power supply VCOM is connected to the common electrode of the liquid-crystal cell 2. The level of a voltage generated by the driving power supply VCOM changes in a manner interlocked with the pre-charging driving signal CS.
In addition, the pixel unit 1 employs NMOS transistors Q3 and Q4 also serving as a switch circuit adopting a double-gate technique. This switch circuit is a switch for selecting the memory mode. A gate signal RM turns on the NMOS transistors Q3 and Q4. The NMOS transistors Q3 and Q4 connect an NMOS Q5 and an NMOS Q6 to the liquid-crystal cell 2 and the holding capacitor Cs. The NMOS Q5 or Q6 selects and outputs the driving signal FRP or XFRP respectively in accordance with the state of a memory unit 3 shown by a dashed-line block in FIG. 23. As shown in FIG. 24B, the driving signal FRP has the same phase as the driving signal CS related to pre-charge processing. As shown in FIG. 24C, on the other hand, the driving signal XFRP has a phase opposite to that of the driving signal CS. In this way, as a substitute for the switch circuit employing the NMOS transistors Q1 and Q2 in the analog driving mode, the switch circuit employing the NMOS transistors Q3 and Q4 can be activated in the memory mode for driving the liquid-crystal cell 2.
It is to be noted that the memory unit 3 has an SRAM (Static Random Access Memory) configuration including a CMOS inverter having an NMOS transistor Q7 and a PMOS transistor Q8 as well as a CMOS inverter having an NMOS transistor Q9 and a PMOS transistor Q10. The gate of the NMOS transistor Q7 is connected to the gate of the NMOS transistor Q8 whereas the drain of the NMOS transistor Q7 is connected to the drain of the NMOS transistor Q8. By the same token, the gate of the NMOS transistor Q9 is connected to the gate of the NMOS transistor Q10 whereas the drain of the NMOS transistor Q9 is connected to the drain of the NMOS transistor Q10. The memory unit 3 is connected to the signal line SIG through an NMOS transistor Q11 turned on by a gate signal GATED and serves as a memory used for storing the logic level of the signal line SIG. The memory unit 3 outputs an output signal RAM representing the stored logic level of the signal line SIG and also outputs an inverted output signal representing the inverted logic level of the output signal RAM.
The inverted output signal is supplied to the gate of the NMOS transistor Q5 whereas the output signal RAM is supplied to the gate of the NMOS transistor Q6. Since the logic level of the inverted output signal is the inverted logic level of the output signal RAM, only either the NMOS transistor Q5 or the NMOS transistor Q6 is turned on to supply either driving signal FRP or XFRP to the switch circuit employing the NMOS transistors Q3 and Q4.
By the way, as described above, since the pixel unit 1 shown in FIG. 23 as a pixel unit in the hybrid system employs switch circuits for switching the gradation setting operation from the memory mode to the analog driving mode and vice versa, the pixel unit 1 has a problem that the number of transistors and the number of scan lines are large, making the configuration complicated. In addition, the pixel unit 1 also has another problem that the opening window of the liquid-crystal cell 2 is narrow.
In the following description, Japanese Patent Laid-open No. Hei 9-243995 mentioned above is referred to as patent document 1.